Simulating a VHDL/Verilog code using Modelsim SE.

Write, Compile, and Simulate a Verilog model using ModelSim

Getting started with VLSI and VHDL using ModelSim | Beginner's Guide

How to Compile UVM Library for Questa Modelsim 2020?

Implementation of Basic Logic Gates in ModelSim using VHDL

VHDL/Verilog Functional and Timing Simulation Tutorial (Xilinx and Modelsim seemless integration

Verilog Simulation of 4-bit Multiplier in ModelSim | Verilog Tutorial