As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron ...

Editor's Note: In Part I of this series,consultant and ASIC designer Tom Moxon outlined some of the challenges faced in deep submicron ASIC design and discussed the current trends in Virtual Silicon ...

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power.

In the IC design flow, design-for-test is often an afterthought. First, the design is coded, then simulated, then synthesized, and only after all that - usually months into the design cycle - it's ...

In the real world of electronic product design, time-to-market can have a large impact on success. To facilitate production speed, RTL from existing projects is often recycled for use in the new ...