EDN

FPGA Simulation

All the articles in FPGA Simulation meet three criteria: 1. The articles on this site are short, they are 1,000 words or less. Because if you can’t say it in 1,000 words, then you don’t know exactly ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
Nasdaq

Lattice Diamond Software Tool Delivers New Enhancements for FPGA Design, Simulation, and Verification

HILLSBORO, Ore.--(BUSINESS WIRE)-- Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced availability of the latest version of its popular FPGA design ...
New Electronics

HES-DVM simulation acceleration flow for Microchip FPGA designs

Aldec, an expert in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM simulation acceleration flow for Microchip’s PolarFire, ...
Electronic Design

OPAL-RT Technologies supports FPGA motor simulation

May 12, 2014. OPAL-RT Technologies has created a suite of tools to make FPGA-based simulation accessible to engineers developing controllers for electric drives. A press release from PRNewswire points ...
New Electronics

Aldec fpga simulation technology added to Altium Designer

Altium and Aldec have signed an OEM agreement that adds Aldec's fpga simulation capabilities to Altium Designer. The agreement adds an extra dimension for electronics designers working with fpgas and ...
Semiconductor Engineering

Automation And Fault Simulation Of Safety-Critical FPGA Designs

Functional safety is a major challenge for field programmable gate arrays (FPGAs) and other semiconductor designs. Safety requirements go beyond traditional verification, which focuses on design bugs.
Electronic Design

Verification Techniques For FPGA Designs

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...
Design-Reuse

Aldec unveils Xilinx UltraScale FPGA-based prototyping board enabling Simulation Acceleration and Emulation with the latest release of HES-DVM

Henderson, Nev., Feb. 28, 2017 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, unveils the latest HES™ prototyping board ...
Semiconductor Engineering

HDL Simulation Acceleration Solution For Microchip FPGA Designs

A way to accelerate a HDL simulation for a system FPGA design that includes the custom logic and reused IP cores where the testbench executes in the simulator and the synthesizable parts of the design ...
EDN

Arrgghh! My FPGA’s not working: Problems with the *RTL*

Maybe you're an ASIC designer forced by short product lifecycles to move into FPGAs. Or perhaps you're a team leader whose latest project requires chip-level integration, and an FPGA implementation ...
Design-Reuse

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

The latest release of HES-DVM™ provides a simulation acceleration flow, providing significant RTL simulation speed-up of designs targeting Microchip FPGA devices. Henderson, NV, USA – November 3, 2020 ...