For more than four decades, scan technology has somehow eluded the radar screen of the IC test industry. As test continues to evolve and make significant newsworthy changes, scan has maintained a ...

The complicated silicon defect types and defect distribution of new IC manufacturing technologies can result in very low yield for new designs and technology nodes. During technology qualification ...

In the modern era, where meeting high performance and low power targets for any complex SoC (System on Chip) is very tough, testing the SoC has become even more challenging. The purpose of several DFT ...

Scan insertion to improve test coverage and reduce test pattern volume is very common in today’s DFT tools. All of the major ATPG tool vendors (Synopsys, Cadence, and Mentor) offer this approach in ...

At times physical design engineers find it difficult to relate with the additional timing modes introduced in PnR due to DFT insertion. These additional timing modes and related issues could be ...

For advanced technologies, the industry is seeing very complicated silicon defect types and defect distribution. One consequence is that scan chain diagnosis becomes more difficult. To improve the ...

A new concept can execute the same boundary scan test pattern on various ATE systems without modification. Boundary scan is well established and widely used for various board- and system-level test ...

IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...

A new online tool developed by the International Union for Conservation of Nature (IUCN) and social enterprise Searious Business could help stem the massive tide of microplastics entering the world’s ...

A program that Walmart piloted and axed is finding itself right at home at Sam's Club. Scan & Go lets shoppers avoid using a traditional checkout. Using a phone or mobile device, customers scan ...