EDN

System Compiler Adds Support for Mixed-Language Simulation with Verilog and VHDL

San Jose, CA – February 20, 2001 – C Level Design, Inc. today announced a fully automated Verilog Programming Language Interface (PLI) and VHDL Foreign Language Interface (FLI) code generators to ...
Design-Reuse

Avery rolls automation tool, simulator into one

ANDOVER, Mass. — Avery Design Systems has folded a Verilog and C-language testbench-automation tool that works with third-party simulators into its TestWizard offering. The capability had been bundled ...
New Electronics

Verilog based language enables design of DNA circuits

Biological engineers at MIT have created a programming language based on Verilog that allows complex DNA encoded circuits to be designed rapidly. These circuits can be used to give new functions to ...