Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...

Designers are using every design trick to reduce power in a 3G chip design. But, while cutting power, these tricks can create static timing analysis problems. Here's a look at how designers can close ...

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address ...

The Tekron TTM 01-G GNSS clock was tested in a simulated mobile application at 300 km/h, and found to maintain sub-100 nanosecond timing accuracy, and position accuracy within 10 meters. By default, ...

As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, ...

Clock path has always been one of the most critical as well as complex components of timing analysis in synchronous design. With increasing complexities in both functionality as well as test ...

Ever wondered how much timing margin your system really has? You’ve probably asked some questions along these lines, such as: Does my crystal really need 20 parts-per-million (ppm) accuracy? What if ...

The basic considerations when choosing a timing solution for today’s technologies. The difference between a crystal oscillator and an integrated clock device. Use cases and performance factors for ...