Electronic Design

FPGA Design Suite Builds In Timing Analysis With Native Support For SDC Format

With FPGAs pushing aside ASICs in many complex designs, the limits of traditional FPGA timing-analysis tools are being stressed to the breaking point. So if you want to use today's high-end FPGAs in ...
EDN

Timing analysis tool expands FPGA and board design flows

Chronology has expanded its interactive timing analysis and timing diagram product – TimingDesigner – to include tighter integration with vendor-specific board design and FPGA flows. TimingDesigner ...
Electronic Design

Timing Analysis Rounds The Corner To Statistics

In a perfect world, fabrication of silicon ICs would be a perfectly predictable process. Not only would every chip be absolutely identical, but there would be no variations from wafer to wafer, or lot ...