EDN

Design for test boot camp, part 1: Scan test

My colleagues from Mentor Graphics, Ron Press, Martin Keim, and I often write about various aspects of digital IC test. If you started following the Test Voices blog when it was part of Test & ...
EDN

Hierarchical test improves pattern application efficiency

For over 15 years, I've been a big proponent of hierarchical test. Hierarchical test is the commonly used term for creating DFT (design-for-test) features and test patterns at lower level circuit ...
Design-Reuse

Configurable VESA - VGA and DVI Test Pattern Generator

This paper is presented with the Video Graphics Array (VGA) and Digital Visual Interface - Digital (DVI-D) test pattern generator solution with display monitor timing specification as per the Video ...
Electronic Design

Reduce Test/Diagnosis Cost with Optimized Scan-Pattern Ordering

Download this article in PDF format. Finding the right balance among test cost, test quality, and data collection for running diagnosis requires consideration of several competing factors. Luckily ...
Electronic Design

Test Pattern Compression Saves Time and Bits

Test compression sounds like magic. Read on to learn how this trick is done. Large, complex ICs are viable because their design meets test as well as functional requirements. Design for test (DFT) was ...