New research paper titled “Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification” from researchers at University of Bristol and Infineon Technologies. “Constrained ...

A newly drafted IEEE standard will bring more consistency to defect metrics in analog/mixed (AMS) designs, a long-overdue step that has become too difficult to ignore in the costly heterogeneous ...

In my May 2020 CW column, I introduced a new test method for measuring the fracture toughness within the facesheet-to-core interface region of sandwich composites. This proposed test method, referred ...

When asked, many engineers will say that the goal of a test plan for a PCB is full or 100% test coverage. When pressed further, they usually admit that 100% test coverage is virtually impossible to ...

System-level test (SLT), once used largely as a stopgap measure to catch issues missed by automated test equipment (ATE), has evolved into a necessary test insertion for high-performance processors, ...

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...

With more than 20% of organizations deploying updates multiple times per day, according to my company's study, the complexity of test authoring has grown significantly. Test authoring is the process ...