Each new manufacturing process generation brings with it a whole new set of challenges. In an era of multimillion-gate complexity and increasing density of nanometer manufacturing defects, a key ...

Design automation is the key to the development of very large ICs. Optimizing the connection and layout of millions of gates to efficiently perform complex functions is not a job to which humans are ...

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...

Both launch-off-shift (LOS) and broadside-transition-pattern techniques are finding use in the at-speed test of devices fabricated in 130-nm processes and below. The broadside-transition-pattern ...

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Today’s highly complex and large system on chip (SoC) devices and systems present many challenges to be addressed from manufacturing tests to the field while meeting stringent requirements for test ...