EDN

Synthesis-friendly RTL called key to first-pass design

SAN MATEO, Calif. — To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly. That was the bottom-line ...
EDN

Control Synthesis Output with Combinatorial Logic in Procedural Code

While it is tempting to write RTL and let the synthesis tool take over, this isn’t the best way to get the results we want. In this article, we’ll learn how to create complex combinatorial code in ...
Electronic Design

Tool Generates RTL Code From Untimed C++

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool, Mentor Graphics now offers the core ...
Semiconductor Engineering

Balancing Leakage Reduction with Correctness Preservation in RTL Code Generation (Univ. of Central Florida)

A new technical paper titled “CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage” was published by researchers at University of Central Florida. “Large Language Models ...
Semiconductor Engineering

Three Key Aspects Of IP Quality

It’s no secret that today’s huge system-on-chip (SoC) projects require massive amounts of design reuse. No team, no matter how talented, can design a billion or more gates from scratch. They use ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...