EDN

Researchers call for fundamental shift in timing analysis

MONTEREY, Calif. — Calling for a new approach to the design of digital circuits, researchers at the ACM/IEEE Tau workshop here this week (Dec. 2-3) presented strong arguments for a move to statistical ...
EDN

Static crosstalk analysis assures silicon success

With the rapid move to ultradeep submicron designs and feature size processes of 0.13 micron and below, ensuring the integrity of signals as they traverse conductors on a chip is becoming a challenge.
Electronic Design

Timing Checks Go Full Chip

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...
Semiconductor Engineering

Closing The Post-Silicon Timing Analysis Gap

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...