EDN

Timing tool is both static and dynamic

Santa Cruz, Calif. – Claiming the first hybrid approach to transistor-level timing and crosstalk analysis, Nassda Corp. this week will introduce Hanex, a product that combines static and dynamic ...
Semiconductor Engineering

The Demise Of Static Timing Verification?

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address ...
Business Wire

Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Tempus ™ Power Integrity Solution, the industry’s first comprehensive static timing/signal integrity ...
T&D

GNSS Clock Maintains Sub-100 Nanosecond Timing

The Tekron TTM 01-G GNSS clock was tested in a simulated mobile application at 300 km/h, and found to maintain sub-100 nanosecond timing accuracy, and position accuracy within 10 meters. By default, ...
Electronic Design

Static Timing Analyzer Pounds Out Streamlined 5× Performance Upgrade

With runtimes improved by up to 5 and memory utilization reduced by up to 30% on large designs, the latest version of the TimeCraft static timing analyzer is intended for multimillion-gate designs.
Electronic Design

Static Timing Analyzer Addresses Corner-Case Explosion

Static timing analysis (STA) is used throughout chip design. It’s employed for the creation of basic constraints in synthesis, for block- and chip-level timing closure in physical implementation, and ...
Semiconductor Engineering

What Happened To Statistical Static Timing Analysis?

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).