Nasdaq

Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC’s N4P Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial ...
SDxCentral

Synopsys 5G SoC enhances 5G development with new RF design flow for TSMC N6RF process

RFICs (Radio Frequency Integrated Circuits) for wireless data transmission systems, such as transceivers and RF front-end components, are becoming more complex based on the demands of our connected ...
TweakTown

Synopsys and Samsung achieve production tapeout of next-gen Exynos SoC on new 3nm process node

Synopsys and Samsung have announced its hit first production tapeout of its next-generation flagship mobile CPU on Samsung Foundry's GAA process. The companies announced that they have achieved ...
Seeking Alpha

Synopsys and TSMC Collaborate to Accelerate 2nm Innovation for Advanced SoC Design with Certified Digital and Analog Design Flows

Design Flow Achieved Multiple Successful Test Chip Tape-Outs on TSMC N2 Process; Broad IP Portfolio in Development to Speed Time to Market Highlights: Synopsys' (SNPS) certified digital and analog ...
EDN

SoC design: What’s next for NoCs?

Today’s high-end system-on-chips (SoCs) rely heavily on sophisticated network-on-chip (NoC) technology to achieve performance and scalability. As the demands of artificial intelligence (AI), ...
Electronic Design

Speeding the Process of Building IPs, Chiplets, and SoCs

How IP-XACT enables tool interoperability, multi-level abstraction, and accurate hardware/software interface alignment through structured metadata. Why integration automation is critical as complexity ...
Business Wire

Intel Foundry and Arm Announce Multigeneration Collaboration on Leading-Edge SoC Design

SANTA CLARA, Calif. & CAMBRIDGE, England--(BUSINESS WIRE)--Intel Foundry Services (IFS) and Arm today announced a multigeneration agreement to enable chip designers to build low-power compute ...
Forbes

Cadence Brings Big Data And AI Analytics To SoC Verification

Forbes contributors publish independent expert analyses and insights. I write about disruptive companies, technologies and usage models. Over the years, the cost of designing a system on chip (SoC) ...
Semiconductor Engineering

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and ...