EDN

How to achieve 1 trillion floating-point operations-per-second in an FPGA

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal ...
EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
Semiconductor Engineering

Achieving Numerical Precision And Design Customization With Flexible Floating-Point IP

As defined by the IEEE 754 standard, floating-point values are represented in three fields: a significand or mantissa, a sign bit for the significand and an exponent field. The exponent is a biased ...
New Electronics

Tachyum successfully tests BF16 on Prodigy FPGA hardware

BF16, or bfloat16, is a shortened floating point data type based on the IEEE 32-bit single-precision floating point data type (f32) and is used to accelerate machine learning by reducing storage ...
Design-Reuse

ARM Announces Vector Floating-Point Coprocessor for ARM9E-S Cores

New Floating-Point Coprocessor from ARM targets automotive and industrial control applications EMBEDDED PROCESSOR FORUM, San Jose, Calif. - June 12, 2001 - ARM [(LSE:ARM); (Nasdaq:ARMHY)], the ...
The Next Platform

Broader Reduced Precision HPC on Horizon

The rise in interest in deep learning chips for training and inference has reignited interest in how reduced precision compute can cut down on energy, bandwidth, and other constraints inherent to ...
insideHPC

With Accelerator SOC, South Korean Institute Says Country on Track to Become 5th HPC Manufacturer

The Electronics and Telecommunications Research Institute (ETRI) of South Korea announced that a group of South Korean researchers has developed the country’s first floating point accelerator chip for ...