As design size and complexity increase, so too does the cost of test. Both the design community and the test industry are looking at various approaches to lower the cost of manufacturing test. This ...
In recent years, boundary scan has transformed itself. JTAG started more than a decade ago as a simple structural interconnect test technology. It now is a foundational embedded infrastructure capable ...
Design for test (DFT) has been around since the 1960s. The technology was developed to reduce the cost of creating a successful test for an IC. Scan design, fault models, and automatic test pattern ...
As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...
Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping ...
Richardson, Texas—A product called DFT Analyzer from ASSET InterTech, Inc., a maker of IEEE-1149.1/JTAG boundary-scan test and ISP (in-system programming) tools, promises to reduce manufacturing and ...
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