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Intel, Synopsys, TSMC All Unveil Record Memory Densities

Last week at the IEEE International Solid State Circuits Conference, two of the biggest rivals in advanced chipmaking, Intel ...
Semiconductor Engineering

Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh Environments

On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is ...
EDN

Changes force radical rethink of ASIC SRAM

SAN MATEO, Calif. SRAMs embedded in cell-based chip designs are, after years of relative stasis, in the midst of a shakeup. A convergence of factors, both architectural and process-related, is forcing ...
Electronic Design

Should Dual Rail Go Mainstream in Deep Nanometer Era?

Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the ...