Electronic Design

A Good Methodology Helps Design Teams Check RTL Code

Many of today's large, complex designs can contain thousands of lines of Verilog or VHDL code. Quite often, teams of engineers—with some members possibly situated in disparate locations worldwide—will ...
EDN

Synthesis moves a step above RTL, aiding ESL design

Santa Cruz, Calif. — Three vendors promise to lift ASIC and FPGA designers above today's RTL design methodologies with high-level synthesis tools they will roll out this week. Though the companies all ...
EDN

Defining the TLM-to-RTL Design Flow

As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron ...
Semiconductor Engineering

RTL Design-for-Power Methodology

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power.