If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz.

Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...

C-level hand-off—generating the entire RTL design from C-language code written by algorithm developers—has been one of the most elusive goals of the EDA industry. A few design teams, often working on ...

As discussed in Part 1, this article proposes four steps to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach to migrate to SystemVerilog. In Part 1 we ...

Much of what's emerged from the Cadence/Verisity merger has been aimed toward addressing the lack of predictability in the verification process. Cadence has spent a good deal of time and energy ...

The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage ...