Electronic Design

A Good Methodology Helps Design Teams Check RTL Code

Many of today's large, complex designs can contain thousands of lines of Verilog or VHDL code. Quite often, teams of engineers—with some members possibly situated in disparate locations worldwide—will ...
Electronic Design

Tool Generates RTL Code From Untimed C++

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool, Mentor Graphics now offers the core ...
EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
Semiconductor Engineering

Choosing The Right Superlinting Technology For Early RTL Code Signoff

No one can afford to go through weeks of verification only to discover problems in the register- transfer level (RTL) code that might not be functionally wrong, but do not follow established rules for ...
Semiconductor Engineering

Balancing Leakage Reduction with Correctness Preservation in RTL Code Generation (Univ. of Central Florida)

A new technical paper titled “CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage” was published by researchers at University of Central Florida. “Large Language Models ...