But taking a voltage-controlled oscillator at 100 MHz (nominal) and dividing its output by 100 will give you a signal you can lock to a 1 MHz crystal oscillator which is, of course, trivial to build.

The real "showstopper" in a standard digital PLL is the interaction between the loops. In a typical design, the Phase Detector and the Frequency Detector run simultaneously.

In this paper an All Digital phase locked loop is proposed. This PLL can accomplish faster phase lock. Additionally, the functions of frequency comparator and phase detector have been improved and are ...

Some brief theory and typical measurements of phase noise. How to produce the lowest phase noise at a PLL output. A standard design procedure for a typical Type 2, second-order loop. As stated in ...

While analog phase-lock loops (PLLs) still have a home in communication equipment, there is a clear shift in the sector toward implementing digital PLLs (DPLLs) in comm ASIC designs. For example, in ...

TI offers clock and timer solutions with Phase Lock Loops (PLLs) including PLL clock buffers, PLL clock synthesizers, PLL based multipliers, zero delay PLL clock drivers and more. Whether you need ...

This three-part series discusses how phase noise in general is modeled and simulated, and how RF component phase noise propagates through a PLL to determine its output phase noise. Some brief theory ...

This article discusses the various control mechanisms for MEMS Coriolis Vibratory Gyroscopes (CVG), and how they can be applied with the commercial off-the-shelf HF2LI Lock-in Amplifier. A MEMS ...