EDN

DDR PHY interface spec to be released at Denali’s MemCon

SAN FRANCISCO — A DDR PHY Interface (DFI) specification, seeking to define a common interface between memory controller logic and the PHY interface, is set to be unveiled next week at an event hosted ...
EDN

DDR PHY Interface Specification Version 2.1 focuses on low power features

Winchester, UK – As one of the DDR PHY Interface (DFI) specification participating members, Denali Software, Inc., has announced the availability of the preliminary version of the DFI specification ...
Business Wire

Rambus Achieves Industry-Leading GDDR6 Performance at 18 Gbps

Rambus GDDR6 Memory PHY has achieved the industry’s highest 18 Gbps performance Leading-edge memory PHY IP is four-to-five times faster than current DDR4 solutions Offers a complete and optimized ...
Business Wire

MIPI M-PHY Update Doubles Peak Data Rate for Next-Generation Flash Memory Storage Applications

PISCATAWAY, N.J.--(BUSINESS WIRE)--The MIPI Alliance, an international organization that develops interface specifications for mobile and mobile-influenced industries, today announced a major update ...
Design-Reuse

Ingot Announces New Memory Controller PHY IP

Santa Clara, Calif -- Nov 21, 2005 - Ingot Systems, the leading provider of Electronic Design Solutions, today announced the immediate availability of the IP4010, a new DDR/SDR SDRAM PHY solution.
Semiconductor Engineering

Pushing The Envelope With HBM2E Memory

In September, Rambus announced the achievement of reaching 4 gigabits per second (Gbps) operation with our HBM2E memory interface. This milestone was demonstrated in silicon and required mastering ...
Semiconductor Engineering

The Hunt For A Low-Power PHY

The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budget. What can be done to prevent a PHY limit? Physics ...