LEUVEN, Belgium — This week, at SPIE 2023 Advanced Lithography + Patterning Conference, in San Jose, CA, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, ...

Continued scaling of integrated circuits to smaller dimensions is still a viable way to increase compute power, achieve higher memory cell density, or reduce power consumption. These days, chip makers ...

Major processes in semiconductor wafer fabrication: 1) wafer preparation, 2) pattern transfer, 3) doping, 4) deposition, 5) etching, and 6) packaging. The process of creating semiconductors can be ...

Researchers review AI-powered inverse lithography, showing how deep learning boosts chip patterning precision and efficiency while facing scaling challenges. Computational lithography optimizes the ...