New KV cache compaction technique cuts LLM memory 50x without accuracy loss

MIT researchers developed Attention Matching, a KV cache compaction technique that compresses LLM memory by 50x in seconds — ...

SOCAMM2 Is The Memory Standard AI Is Looking For

AI infrastructure can't evolve as fast as model innovation. Memory architecture is one of the few levers capable of accelerating deployment cycles. Enter SOCAMM2 ...
EDN

Last-level cache has become a critical SoC design element

LLC, positioned between external memory and internal subsystems, stores frequently accessed data close to compute resources.

Huawei Launches AI Data Platform to Bridge Models and Business Value

At the Huawei Product & Solution Launch during MWC Barcelona 2026, Yuan Yuan, President of Huawei Data Storage Product Line, officially launched Huawei's AI Data Platform. The platform integrates ...

Running AI models is turning into a memory game

When we talk about the cost of AI infrastructure, the focus is usually on Nvidia and GPUs -- but memory is an increasingly important part of the picture.
The Manila Times

Micron Sets New Benchmark With the World's First High-Capacity 256GB LPDRAM SOCAMM2 for Data Center Infrastructure

Micron Technology, Inc. (Nasdaq: MU) today extended its leadership in low-power server memory by shipping customer samples of the industry’s highest-capacity LPDRAM module - 256GB SOCAMM2. Enabled by ...
SiliconANGLE

CXL memory: The key to unlocking high-performance computing in modern data centers

As the demand for real-time data processing escalates, the technology behind Compute Express Link, known as CXL, is emerging as a critical solution for modern data centers. CXL memory is one solution ...
DatacenterDynamics

Reshaping data infrastructure to help carriers digitally transform

At MWC Barcelona 2026 the president of Huawei Data Storage Product Line shared Huawei's key insights and innovations ...
EDN

Using L1 Cache on PIC32MZ Devices

The purpose of this application note is to familiarize the reader with the Level 1 (L1) CPU cache implementation in the PIC32MZ device family by bringing awareness to the hazards that can occur in a ...