EDN

Synopsys’ New DesignWare DDR Explorer Tool Delivers Up to 20 Percent Improvement in DDR Memory Subsystem Efficiency

DesignWare DDR Explorer enables designers to optimize memory subsystems for power, performance and cost through a graphical simulation and analysis environment Explore and adjust Synopsys' DesignWare ...
EDN

AccelChip IP-Explorer removes trial and error of DSP algorithm optimization

AccelChip, provider of IP and software for MATLAB and Simulink DSP algorithms announced technology it says provides unparalleled automation for DSP applications in FPGAs and ASICs. AccelChip DSP ...
Electronics Weekly

Canadian tool speeds analogue chip design

Canadian firm Analog Design Automation (ADA) has released tools that aim to speedanalogue chip design. ADA’s two products are Creative Genius, which compiles a database of analogue IP,and IP Explorer ...
IPWatchdog

ipAwarenessAssessment: Inventors and Business Owners Should Start Their IP Journey with this USPTO-NIST Tool

“Taking any of these assessments should be the first step in a business owner’s or inventor’s journey in determining how well they know their own IP assets, exposure thereof, potential mechanisms to ...
Electronic Design

Synthesis Tool Suite Speeds DSP Design

With multiple tools being brought to bear on the process of DSP design and synthesis, the AccelDSP Synthesis 8.1 tool and AccelWare DSP libraries of algorithmic IP make short work of FPGA-based DSP ...