Design-Reuse

Xilinx ISE Design Suite 12 Enables Up to 30% Dynamic Power Reduction with Intelligent Clock-Gating Technology

AMBA 4 AXI4 IP Support and Innovations in Design Preservation Combined with ISE Power Optimization to Deliver New Levels of Productivity for Virtex-6 and Spartan-6 FPGAs SAN JOSE, Calif., May 3, 2010- ...
Electronic Design

1.5-GHz FPGA Takes Clock Gating To The Max

Flexibility is key to FPGA success, but speed is equally important. Achronix almost triples the throughput of the system by taking clock gating to the extreme. The Achronix Speedster FPGAs use a ...
EDN

Sequential clock gating maximizes power savings at IP level

Power Management is one of the major chip design challenges amongst all the dimensions of the design cycle. It poses problems for packaging, portability, & reliability (PPR), e.g.,“high system cost of ...
EDN

Xilinx ISE Design Suite 12 Enables Up to 30% Dynamic Power Reduction with Intelligent Clock-Gating Technology

SAN JOSE, Calif., May 3 /PRNewswire/ — Xilinx (Nasdaq: XLNX) today introduced the ISE® Design Suite 12 software to enable breakthrough optimizations for power and cost with greater design productivity ...