Los Altos, Calif. – True Circuits Inc., a provider of analog and mixed-signal intellectual property (IP), will introduce two phase-locked-loop macros this week for 0.18- and 0.13-micron CMOS ASICs.
The PLL circuit shown in Figure 1 uses a 13 GHz Fractional-N synthesizer, wideband active loop filter and VCO, and has a phase settling time of less than 5 μs to within 5° for a 200 MHz frequency jump ...
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