EDN

Designing DDR3 SDRAM controllers with today’s FPGAs

The recently introduced DDR3 SDRAM technology paves the way to higher data rates (from 800 Mbps to 1600 Mbps) and provides higher performance for many systems that depend on data, video, or packet ...
EDN

DDR3 memory interface controller IP speeds data processing applications

DDR3 memory systems can provide a significant performance boost to a variety of data processing applications. However, compared to previous generations (DDR and DDR2), DDR3 memory devices have some ...
Design-Reuse

Lattice Announces Industry's Fastest Low-Cost FPGA DDR2 Controller

Lattice Offers the First 533 Mbps DDR2 SDRAM Controller for its Low-Cost LatticeECP2 and LatticeECP2M FPGAs as well as its LatticeSC FPGA Family low-cost FPGA families, as well as its high-end ...
Business Wire

Everspin Releases Design Guide for using 1 Gb STT-MRAM with Xilinx DDR4 FPGA Controller

CHANDLER, Ariz.--(BUSINESS WIRE)--Everspin Technologies, Inc. (NASDAQ: MRAM), the world's leading developer and manufacturer of Magnetoresistive RAM (MRAM), today announced a comprehensive design ...
Nasdaq

MoSys Launches New QUAZAR QPR Family of Low Cost, Quad Partition Rate SRAM Memory ICs Targeted for Accelerating INTEL and XILINX FPGA Designs

QDR Level Performance - Replaces up to 8X QDRs - Capacities of 576Mb or 1Gb in Single Device Costing Less Than $200 in Volume Quantities SAN JOSE, CA / ACCESSWIRE / July 15, 2020 / MoSys, Inc. (NASDAQ ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...
EurekAlert!

Advanced NVMe controller technology for next generation memory devices

KAIST researchers advanced non-volatile memory express (NVMe) controller technology for next generation information storage devices, and made this new technology named 'OpenExpress' freely available ...