Hackaday

JTAG Dongle Pushes Code To FPGA After Bootup

This gnarly beast has near-magical qualities. [Sprite_TM] patched it together as a dongle which attaches to a JTAG header (we’re fairly certain this is not a standard footprint for that interface ...
EDN

Generate FPGA designs from M-code

DSP systems are best described by using a combination of both graphical-and language-based methods. The MathWorks, an industry leader in DSP modeling software, caters to this dichotomy by providing a ...
Electronic Design

Programming FPGA Systems: Code Conversion

Code Conversion On the left side below is the ANSI-C software code that makes the call to the C Hough function. The input to the Hough function is the image to be processed (TileIn). The output of the ...
Electronic Design

FPGA Design Flow Takes Simulink Code Into Synthesis

Thanks to collaboration between The MathWorks and Mentor Graphics, MathWorks’ Simulink HDL Coder users gain a smooth path into synthesis. Mentor’s Precision Synthesis tool now supports HDL generated ...
Design-Reuse

A practical approach to reusing HDL code in FPGA designs

From the very first day that you learn a new hardware description language (HDL), you reuse code. Initially, this might involve copying an example and modifying it in order to learn and expand your ...
Hackaday

FPGA-and-Pi Colossus Smashes Your Codes!

If it were sixty years ago, and you were trying to keep a secret, you’d be justifiably glad that [Ben North] hadn’t traveled back in time with his Raspberry-Pi-and-FPGA code-breaking machine. We’ve ...
EDN

Timing Closure on FPGAs

Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer ...
Geeky Gadgets

Intel Cyclone 10 FPGA and STM32H7 MCU combined to create USB2IO high-speed interface explorer

MCU – STMicro STM32H743 Arm Cortex-M7 @ 480MHz CPU clock An external 64MB QSPI flash for extra FPGA code storage; FPGA – Intel Cyclone 10LP (10CL040) with 40k logic elements, 1,134 Mbit embedded ...
Design-Reuse

Developing processor-compatible C-code for FPGA hardware acceleration

FPGAs are becoming increasingly popular with software teams to accelerate critical portions of their code. In most cases these teams already have processing stacks and applications written in C that ...
TechRepublic

Design and Verification of VHDL Code for FPGA Based Slave VME Interface Logic

Versa Module Europa (VME) bus is used in various applications in order to ensure safety and security. VME64x based Real Time Computer (RTC) system with various types of Input /Output (I/O) hardware ...