Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

How formal verification is able to find bugs before signoff. Formal verification’s ability to mathematically prove exhaustively that a chip design meets a set of assertions. Formal techniques are ...

This course covers the systematic design of real-time digital systems and verification techniques using field-programmable gate arrays (FPGAs). The course presents a top-down design methodology, where ...

It’s often said that “the secret to a good marriage is good communication” but it’s equally true that good communication is the secret to a successful IP or system-on-chip (SoC) project. Such projects ...

Chip designs are optimized for lower cost, better performance, or lower power. The same cannot be said about verification, where today very little effort is spent on reducing execution cost, run time, ...

A “shift-left” PCB design verification solution within the engineer’s authoring environment is the industry’s first of its kind, claims developer Mentor, a Siemens business. This new Xpedition ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

I'm fast approaching the one year mark with my current employer since I graduated last year. Previously, I did three four month work terms with them and they were for the most part interesting. I took ...

Low power design techniques ” As designs are moving towards smaller and smaller technologies (90nm, 65nm ), leakage current has become significant and contributes to overall power. Designs are using ...

When The MathWorks introduced Matlab technical-computing software more than 20 years ago, many of the first users were control-system designers. Anyone who had laboriously inverted matrices by hand to ...