Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Its use results in faster development, cleaner testbenches, and a modern software-oriented approach to validating FPGA and ASIC designs without replacing your existing simulator.

It’s often said that “the secret to a good marriage is good communication” but it’s equally true that good communication is the secret to a successful IP or system-on-chip (SoC) project. Such projects ...

This is the world’s first AI-powered super agent from Cadence that autonomously creates and verifies designs from specifications and high-level descriptions ...

To fill the talent gap, CS majors could be taught to design hardware, and the EE curriculum could be adapted or even shortened.

This course covers the systematic design of real-time digital systems and verification techniques using field-programmable gate arrays (FPGAs). The course presents a top-down design methodology, where ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

Editor Bill Wong talks with Mentor’s David Wiens about its unique “shift-left” PCB design verification platform for early prototyping and reduced re-spins. A “shift-left” PCB design verification ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...

Aparna Mohan pioneered a groundbreaking verification methodology for security-critical semiconductor designs that has transformed how the industry approaches security verification, yielding ...