Business Wire

Mentor Graphics Adds Major New Design Rule Checking Product to HyperLynx Suite

WILSONVILLE, Ore.--(BUSINESS WIRE)--Mentor Graphics Corporation (NASDAQ:MENT) today announced the release of a major new product in the HyperLynx® suite, the market-leading, high-speed analysis ...
Business Wire

Aldec Sets a New Paradigm with a Single Platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc. announced today the latest release of its mixed-language Design Rule Checking (DRC) and Clock Domain Crossing (CDC) verification platform, ALINT-PRO™ 2017 ...
Electronic Design

Design-Rule Checker Sports Foundry Compatibility

Advances in design checking capability, including foundry-compatible design-rule checking (DRC) and background DRC, are among the features of HiPer Verify, the first tool in a line of IC layout and ...
New Electronics

Siemens and TSMC extend partnership on AI‑driven semiconductor design

Siemens has announced an extension of its long‑running collaboration with Taiwan Semiconductor Manufacturing Company (TSMC), expanding joint efforts to advance artificial intelligence‑powered ...
EDN

Mentor Graphics addresses designs with interactive DRC software

Mentor Graphics has developed an interactive version of its Calibre design-rule checking (DRC) software to address analogue and memory designs, using more precise rules to identify common design ...
Semiconductor Engineering

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster

Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a ...
EDN

LG Adopts In-Design Physical Verification with IC Compiler and IC Validator after Multiple Successful Tapeouts

Synopsys' In-Design physical verification with IC Validator and IC Compiler place-and-route solution accelerates LG Electronics' manufacturing closure by two weeks Multiple successful tapeouts using ...
Semiconductor Engineering

Let’s Do The (IC Design) Time Warp Again

For the most part, we’ve all been doing integrated circuit (IC) and system-on-chip (SoC) layout the same way for decades. Designers put together the design, be it intellectual property (IP), block, or ...
Electronic Design

The ASIC Vendor's View Of RTL Rule Checking

Frequently, the customer netlists sent to ASIC vendors' design center engineers for physical implementation are riddled with problems. "If you have timing or congestion problems in implementations, it ...