Electronic Design

Signoff Evolves From Design-Rule Checking To Yield Analysis

IC designers are a lucky bunch. Through many years of semiconductor process evolution, the impact of manufacturing limitations and variations on layout could be encapsulated in relatively simple ...
Business Wire

Mentor Graphics Adds Major New Design Rule Checking Product to HyperLynx Suite

WILSONVILLE, Ore.--(BUSINESS WIRE)--Mentor Graphics Corporation (NASDAQ:MENT) today announced the release of a major new product in the HyperLynx® suite, the market-leading, high-speed analysis ...
EDN

New error comparison scheme proposed for design rule checking flows

BENGALURU, India — With design rule checking becoming hugely complex in the deep sub-micron regime, there is a large run time for physical verification tools, for the number of design rules that must ...
Semiconductor Engineering

Achieve Dramatic Productivity And Turnaround Time Improvements In Early Design Electrical Rule Checking

Early-stage layout vs. schematic (LVS) and circuit verification typically return large numbers of connectivity errors, which can be a critical bottleneck for both LVS and physical verification flows ...
Business Wire

Aldec Sets a New Paradigm with a Single Platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc. announced today the latest release of its mixed-language Design Rule Checking (DRC) and Clock Domain Crossing (CDC) verification platform, ALINT-PRO™ 2017 ...
Semiconductor Engineering

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to ...
Electronic Design

The ASIC Vendor's View Of RTL Rule Checking

Frequently, the customer netlists sent to ASIC vendors' design center engineers for physical implementation are riddled with problems. "If you have timing or congestion problems in implementations, it ...
Tech Xplore on MSN

AI learns to perform analog layout design

Researchers at Pohang University of Science and Technology (POSTECH) have developed an artificial intelligence approach that addresses a key bottleneck in analog semiconductor layout design, a process ...
EDN

Automated DRC violation correction speeds designs to tapeout

No matter how careful chip design engineers are, and regardless of what implementation tools they use, a verification team will always encounter design rule checking (DRC) errors during the signoff ...
Nasdaq

ASE launches its Integrated Design EcosystemTM to enable silicon package design efficiencies that reduce cycle time by half

SUNNYVALE, Calif.--(BUSINESS WIRE)-- Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced the launch of its Integrated ...