Business Wire

Silvaco and OPENEDGES Announce Availability of Integrated DDR Controller and PHY IP Solutions

SANTA CLARA, Calif. & SEOUL, South Korea--(BUSINESS WIRE)--Silvaco, Inc., a leading supplier of EDA software and design IP, today announced a collaboration with OPENEDGES Technology, Inc., a leading ...
EDN

ESC – New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces

Mountain View, Calif. – Synopsys, Inc. today announced the availability of the high-performance DesignWare Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and ...
Electronic Design

PWM Controller IC Aims At DDR Memory Arrays

The IRU3038 synchronous pulse-width modulation (PWM) controller IC handles the termination-voltage requirements of double-data-rate (DDR) memory arrays. By ...
Nasdaq

Microchip Enters Memory Infrastructure Market with Serial Memory Controller for High-performance Data Center Computing

BANGKOK, Thailand, Aug. 8, 2019 /PRNewswire/ -- As the computational demands of artificial intelligence (AI) and machine learning workloads accelerate, traditional parallel attached DRAM memory has ...
TechRepublic

Implementation of DDR SDRAM Controller Using Verilog HDL

Now-a-days, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) has become the most popular class of memory used in computers due to its high speed, burst access and pipeline feature ...
EDN

LSI, Denali Construct DDR Memory Controller Roadmap

LSI Logic reported Tuesday it has inked an agreement with Denali Software Inc. to use the Databahn DDR controller intellectual property (IP) to support its RapidChip Platform ASIC and application ...
Design News

Optimizing LPDDR and DDR Memory for Cutting-Edge Apps

The role of memory to handle an avalanche of data expected in future leading-edge applications such as automotive and artificial intelligence has led to product innovations from several companies, the ...
Electronic Design

A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!

The number of systems-on-a-chip (SoCs) that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to double-data-rate (DDR) SDRAM interfaces such as ...
Semiconductor Engineering

DDR Memory Test Challenges From DDR3 to DDR5

Cloud, networking, enterprise, high-performance computing, big data, and artificial intelligence are propelling the development of double data rate (DDR) memory chip technology. Demand for lower power ...
Semiconductor Engineering

Time For A DDR Background Check

In this month’s blog we continue our discussion of power management, specifically looking at how architects can improve the energy efficiency of their SoC as it uses system memory. In March we teamed ...
Forbes

The Rise Of Memory-Centric Architectures

Many have argued that the processor-centric server architecture of today, where processors and memory are tightly coupled, will be replaced by a memory-centric architecture in which memory is ...