EDN

Use SystemVerilog for coverage metrics

The design-and-verification industry is at the intersection of two important trends in the design and verification of SOC (system-on-chip) devices: the adoption of SystemVerilog HDVL ...
EDN

Using SystemVerilog for functional verification

The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or ...
Design-Reuse

Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP

Technology advances allows for the creation of larger and more complex designs. This poses new challenges, including efforts to balance verification completeness with minimization of overall ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

The result is undesirable and less than adequate performance. For partitioning purposes, a discussion of SystemVerilog can be broken out into four key segments: design, assertions, testbench ...