The power issues encountered by today's mobile phone manufacturers is well documented. With cameras, web browsers, and other processing-intensive tasks entering next-generation phones, designers try ...

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...

Among the perennial challenges of advanced-node IC design is power reduction. Clock trees are now the single largest source of dynamic power consumption, which makes clock tree synthesis (CTS) and ...

Designers are using every design trick to reduce power in a 3G chip design. But, while cutting power, these tricks can create static timing analysis problems. Here's a look at how designers can close ...