Semiconductor Engineering

Effective Clock Domain Crossing Verification

As chips grow ever larger and more complex, gate count and amount of embedded memory grow dramatically. The number of clock domains is also increasing steadily. Several dozen different clocks are ...
EDN

Real Intent announces Meridian clock domain crossing verification software

At the Design Automation and Test Exposition (DATE) conference in Nice today, Real Intent announced Meridian – new Clock Domain Crossing (CDC) verification software. Meridian is a completely new ...
Semiconductor Engineering

Reset Domain Crossing Verification

To meet low-power and high-performance requirements, system on chip (SoC) designs are equipped with several asynchronous and soft reset signals. These reset signals help to safeguard software and ...
EDN

Real Intent Demonstrates Formal Verification Software for Bug Hunting, Verifying Clock Domain Crossing Signals, Assertions and Timing Constraints at EDSFair2008

Real Intent, Inc., the leading supplier of formal verification software for electronic design, will demonstrate its proven formal verification software at the Electronic Design and Solution Fair 2008 ...
WDAF-TV

Accellera Announces the Formation of the Clock Domain Crossing Working Group

ELK GROVE, Calif., Jan. 17, 2023 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design ...
Electronic Design

IC-Design Analyzer Checks Clock-Domain Crossings; Creates Constraints

An increasingly critical area of chip design is that of clock-domain crossings (CDCs), and more than ever CDCs are plaguing FPGA designers. Blue Pearl Software's tools now are friendlier than ever to ...