Electronic Design

Formal Methodology Validates Cache-Coherence Protocol

Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all ...
Semiconductor Engineering

Heterogeneous Cache Coherence Requires A Common Internal Protocol

Machine learning and artificial intelligence systems are driving the need for systems-on-chip containing tens or even hundreds of heterogeneous processing cores. As these systems expand in size and ...
Semiconductor Engineering

Reducing The Cost of Cache Coherence By Integrating HW Coherence Protocol Directly With The Programming Language

A new technical paper titled “WARDen: Specializing Cache Coherence for High-Level Parallel Languages” was published by researchers at Northwestern University and Carnegie Mellon University.
Design-Reuse

Using OCP and Coherence Extensions to Support System-Level Cache Coherence

Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...
Design-Reuse

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for ...
EDN

Memory models for embedded multicore SoCs, Part 5 – Cache performance

Write-through: all cache memory writes are written to main memory, even if the data is retained in the cache, such as in the example in Figure 4.11. A cache line can be in two states – valid or ...