Design-Reuse

VLSI Design: Future of Wireless Communication

As a technology enthusiast, I have always been fascinated by the rapid advancements in the field of wireless communication. The ability to connect with people and devices wirelessly has revolutionized ...
TechRepublic

Low Power VLSI CMOS Design by DCG Technique

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown ...
TechRepublic

Intel’s 45nm CMOS Technology Performance Parameters in VLSI Design

The trend of CMOS technology improvement continues to be driven by the need to integrate more functions within a given silicon area. In this paper, the authors describe Intel’s 45nm technology ...
New Electronics

Cadence open-source PDK and reference design now available for SkyWater's 130nm process

SkyWater Technology has announced that a new SkyWater open-source 130 nm process design kit (PDK) from Cadence Design Systems, will be available in the Cadence VLSI (very large-scale integration) ...
Electronics Weekly

Cadence offers academia PDK for open source 130nm SkyWater process

A PDK for the SkyWater open-source 130 nm process will be available in the Cadence VLSI (very large-scale integration) Fundamentals Education Kit. The kit teaches students how theories and concepts ...
Design-Reuse

SkyWater Announces Availability of Cadence Open-Source PDK and Reference Design for SkyWater's 130 nm Process

BLOOMINGTON, Minn. – November 6, 2023 – SkyWater Technology (NASDAQ: SKYT), the trusted technology realization partner, today announced a new SkyWater open-source 130 nm process design kit (PDK) from ...
EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...