Electronics Weekly

LETI integrates III-V lasers on 200mm wafers using CMOS flow

Leti has integrated hybrid III-V silicon lasers on 200mm wafers using standard CMOS process flow. This shows the way to transitioning away from 100mm wafers and a process based on bulk III-V ...
EDN

Mixed-signal design flow enables RF CMOS chip

Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a ...
sciencex

Towards a process flow for monolithic CFET transistor architectures

—The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) transistor architecture is complex due to the need to vertically separate nMOS and ...
Electronics Weekly

CMOS will cut cost of integrated photonics, says Leti

French research group Leti has demonstrated a III-V semiconductor fabrication technique which it says will simplify the production of lasers. Leti says it has integrated hybrid III-V silicon lasers on ...
EDN

Foundry offers bipolar CMOS DMOS process for power management market

Jazz Semiconductor, an independent wafer foundry focused primarily on specialty CMOS process technologies, today announced the availability of 0.5 micron BCD process technology targeted for power ...
Design-Reuse

Radiation Hardened SRAM Designed by RedCat Devices and Fabricated in TowerJazz's 0.18um Process Flow Withstands 15 Mrad Total Ionization Dose

Developed technology in TowerJazz commercial foundry opens multi-billion markets requiring specific components able to withstand high dose radiation Applications include electronics for communication, ...
Electronic Design

Simplified High-k/Metal-Gate Process Increases Planar CMOS Speed

IMEC, the Belgium-based nanotechnology research center, announced at this week's VLSI Symposium that it has improved the performance of its planar CMOS using hafnium-based, high-k dielectrics and ...