Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

Design for Test (DFT) is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier ...

In the 1990s, Carnegie Mellon researchers created a comprehensive scan-test cost model that demonstrated how design for test (DFT) contributes to profitability (Ref. 1). With scan compression in wide ...

Recent and continuing trends in the semiconductor industry pose challenges to IC test-data volumes, test application times, and test costs. The industry has thus far succeeded in containing test costs ...

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been ...

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

WILSONVILLE, Ore. and SAN JOSE, Calif. -- August 19, 2009 – Mentor Graphics Corporation (NASDAQ: MENT) and LogicVision, Inc. (NASDAQ: LGVN) today announced that LogicVision stockholders have voted ...